Phase lock loops are clock multipliers. For example, an input clock signal oscillating at 10 Mhz can be multiplied by the PLL to yield an output clock signal oscillating at 200 Mhz. Ideally, this clock multiplication would result in a clock signal which is in perfect phase to a reference (i.e., zero static phase error). Any mismatch between the phase of the feedback clock to the reference clock is a phase offset. A diagram of a PLL is shown in FIG. 1.
It is desirable to keep the static phase error to a minimum. For a multiple chip application (e.g., where several PLL chips have one reference that also drives other chips) it is essential for the user to know the expected clock out (i.e., VCO_CLK) phase deviation from one PLL chip to the other.
During PLL lock, the pump currents into the filter will be equal. However, due to mismatch between the P-switch and the N-switch (typically, an NMOS device will transfer more current than a PMOS device since it is a faster switch) the loop has to mismatch the pulsewidth of the pumpup and the pumpdown signals. Another key mismatch concerns the drain to source VDS mismatch between the PMOS/NMOS switches. This is a function of control voltage operating point. This mismatch is linked directly to the reference clock which presents a feedback of the phase offset. The pumpup pulse is mismatched relative to the pumpdown pulse (the phase of REF differs from FB). This difference results in the phase offset.
Static phase error is caused by non-ideal elements in the PLL. Primarily, the charge pump followed by the phase frequency detector may cause static phase error. The PLL will start by locking to the desired frequency. However, due to the non-ideal elements, the PLL may have to shift the phase of the clock relative to the reference to achieve frequency lock. FIG. 2 illustrates such shifting.
Conventional approaches to reducing static phase offset may include (A) cascading PMOS and NMOS switches in order to reduce the drain to source Vds mismatch contribution, (B) implementing PMOS/NMOS switches with larger channel length (which lowers the channel modulation effect) in order to reduce the Vds mismatch contribution, (C) adding static phase offset to the phase frequency detector to cancel the error introduced by the pump, and (D) building differential charge pumps.
The disadvantages of Method A is that the cascading lowers the operating headroom current of the charge pump (i.e., the method can not use large currents). The cascading lowers the operating range (i.e., the output voltage) of the pump (i.e., less range on the VCO input) which can result in a high gain VCO that may be less immune to noise. However, static phase offset is still large (e.g., +/-250 ps at 155 Mhz). The output may be highly dependent on process, temperature, VCC, and output voltage. In order to match the pumpup and the pumpdown pulsewidths, it is essential to keep charge feed through (i.e., current spikes) on the switch to a minimum. This requirement forces the design to utilize small switch devices (i.e., low capacitance devices), and to match the spike characteristics of the PMOS and the NMOS switches, which is not generally an easy task to accomplish.
Method B not only has the disadvantages associated with Method A, but has the further disadvantage that it requires a large channel length that reduces the speed of the PMOS/NMOS switch (due to an increased load).
Method C has the disadvantage that the variation in the static phase offset magnitude over corners is still large. The only improvement provided by Method C is that the static offset is now centered around zero. The added delay in the PFD is highly dependent on proper delay modeling. This approach is highly dependent on process, temperature, VCC, and output voltage. In order to match the pumpup and the pumpdown pulsewidths, it is essential to keep charge feed through (i.e., current spikes) on the switch to a minimum. This requirement forces the design to utilize small switch devices, which have low capacitances, and to match the spike characteristics of the PMOS and the NMOS switches, which is not an easy task to accomplish.
Method D has the disadvantage that it depends on process, temperature, VCC, and output voltage (typically, improved from the single ended). However, such an approach (i) requires stable common mode circuitry, (ii) requires more pump circuitry, (iii) could require additional input buffering, (iv) requires more layout room, and (v) requires careful schematic and layout matching. In order to match the pumpup and the pumpdown pulsewidths, it is essential to keep charge feed through (i.e., current spikes) on the switch to a minimum. This requirement forces the design to utilize small switch devices, which have low capacitances, and to match the spike characteristics of the PMOS and the NMOS switches, which is not an easy task to accomplish.